(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a metal line stacking structure in a semiconductor device.
(b) Description of the Related Art
As semiconductor devices have become more highly integrated and multi-layered, a multi-layer line technology has been introduced as an important manufacturing technology. In such multi-layer line technology, a metal line and a dielectric layer are alternately formed over a semiconductor substrate on which electric circuit elements are formed. The metal line, which are divided by the dielectric layer, are electrically connected together through a contact or via, so that an electric circuit operates.
By applying the multi-layer line technology to a semiconductor device, cross lining has been achieved, so that a freedom of degree and an integration degree in semiconductor device design has been improved, and furthermore, it is possible to decrease a length of a line so that an operation time delay in the line can also be decreased, thereby increasing operation speed of the semiconductor device.
A conventional method for forming a stacking structure of metal lines in a semiconductor device will be explained in detail with reference to the attached drawings. FIGS. 1a to 1f show the conventional method for forming a metal line stacking structure in a semiconductor device.
As shown in FIG. 1a, a metal stacking structure is formed by sequentially stacking a barrier metal (Ti) layer (hereinafter referred to as a first Ti layer) 2, a metal (Al) layer (hereinafter referred to as an Al layer) 3, a titanium (Ti) layer (hereinafter referred to as a second Ti layer) 4, and a titanium nitride (TiN) layer (hereinafter referred to as a TiN layer) 5 on a dielectric layer 1, which is disposed over a semiconductor device substrate and is provided with a contact.
Next, as shown in FIG. 1b, the metal stacking structure is patterned according to a predetermined design and is sintered to form a desired metal line layer. Consequently, TiAl3 6 is generated in some regions between the Al layer 3 and the first and second Ti layers 2 and 4. In the figures, the relative size of the TiAl3 6 has been exaggerated for convenience of explanation.
As shown in FIG. 1c, a dielectric layer 7 is then formed through a HDP (High Density Plasma) method or an SOG (Spin On Glass) method, so that a gap between the metal line layer is filled. Then, an inter-level dielectric layer 8 is deposited over the dielectric layer 7, and is then leveled.
Next, as shown in FIG. 1d, a contact hole 9 is formed in the inter-level dielectric layer 8. In order to decrease the resistance of the contact hole 9 and a resistance change of the contact hole 9 in a wafer, in an etching process to form the contact hole 9, the TiN layer 5 and the Ti layer 4 are over-etched, and etching is terminated after reaching the Al layer 3.
Next, as shown in FIG. 1e, a barrier metal layer, which is a stacking structure of a titanium (Ti) layer 10 and a titanium nitride (TiN) layer 11, is formed on the inter-level dielectric layer 8 and on an inner wall of the contact hole 9 through an in-situ method.
Because the contact holes are now formed deeper and narrower as the integration degree of semiconductor devices has increased, it is preferable that the TiN layer 11 is formed through a CVD (chemical vapor deposition) method in order to increase the bottom step coverage of the barrier metal. Then, as shown in FIG. 1f, a metal (for example, tungsten) layer (hereinafter referred to as a tungsten layer) is deposited in the contact hole 9 through a CVD (Chemical Vapor Deposition) method such that the contact hole 9 is filled with the tungsten. Then, the tungsten layer is polished and leveled through a chemical mechanical polishing (CMP) method until the inter-level dielectric layer 8 is exposed. Therefore, a contact is realized by forming a tungsten plug 12, which is a portion of the tungsten layer, inside the contact hole 9.
The metal line stacking structure in a semiconductor device can be obtained according to the above processes. The above processes are repeated in proportion to a number of metal layers that are needed for a specific semiconductor device.
However, the above conventional method for forming the metal line stacking structure in a semiconductor device has some problems, as follows.
The temperature of the substrate is increased to between 400 and 470 degrees Celsius in order to form the TiN layer 11 in the contact hole 9 through the chemical vapor deposition method. During the process of forming the TiN layer 11 on the high-temperature substrate, thermal energy of the substrate is transmitted to the metal layer, and thereby the metal layer upwardly extrudes through the bottom of the contact hole 9. The extruded metal layer reacts with the Ti layer 10, so that impurities are generated.
For example, if Al is used as the metal layer, TiAl3 is generated, so that a loss of Ti occurs. Therefore, the thickness of a portion of the TiN layer 11 corresponding to this area is relatively thin when compared to other portions.
Such an up-extrusion of the metal layer also occurs in the process of forming the Ti layer 10 if the temperature of the substrate is 280 degrees Celsius or higher.
The thin TiN layer 11 of the barrier metal cannot act as a barrier for a source for forming the metal layer 12. For example, when tungsten is used for the metal layer, the thin TiN layer 11 cannot act as a barrier for an F radical of WF6. Therefore, a TiAlxFy composition, which causes high resistance of the contact hole, is disposed under the TiN layer 11. Thus, the resistance of the contact hole increases, and this may degrade performance of a semiconductor device and cause the same not to operate.
If the temperature of the substrate is decreased in order to solve the above problem, productivity lowers. For example, if the temperature of the substrate is decreased to 400 degrees Celsius from 450 degrees Celsius during the formation of the TiN layer of the barrier metal layer, throughput is decreased by more than 55%, so that efficiency of use of facilities and productivity are decreased.